In U.S. Pat. No. 4,845,667 to Chappell et al., assigned to the same assignee as this application, a pipelined memory chip structure is described wherein the chip is partitioned into 32 8K bit subarrays. The structure uses complementary MOS memory cells, each memory cell composed of six devices. To achieve an improvement in cycle times, the memory array employs localized precharge and input triggered, self resetting circuits. The circuits described therein are able to precharge a block of memory quickly after it has performed its function, in anticipation of the next access.
To assure the success of a memory such as described in the '667 Patent, it is necessary to have a decoder which enables one of 32 blocks of memory to be rapidly selected. Tree circuits enable such decoding, but generally operate at speeds which impair the efficient operation of the memory.
Such tree decoders often use AND circuits which employ complementary MOS, field effect transistors. One such logical AND circuit employs a single N channel CMOS device with the two logical inputs, one applied to a conduction path terminal and another to the gate terminal. The output is taken from the other conduction path terminal. That circuit has a speed advantage since the N channel device conducts as soon as the gate input rises. It also provides reliable operation if the input logic voltages are skewed, as both inputs must transition to the high state for the output to go high. However, since the N channel device operates as a source follower, there is a resulting loss in output level due to the drop across the device.
A P channel implementation of the single device AND circuit is also known which employs input signals which transition in opposite directions. The disadvantage of that circuit is that the input logic signals must pass each other in transitioning from the high to the low state and vice-versa, before the device turns on. This results in an unwanted time delay through the circuit.
Instead of applying a transitioning logic signal to the gate of a P channel device, a dc negative conditioning voltage can be applied and the logic signal applied to a conduction path electrode. The disadvantage to this approach is the circuit's sensitivity to a skew of the input signals. In the event it is desired to deselect the AND circuit, the gate input is raised to render the P channel device nonconductive. However, if the conduction path electrode signal rises before the conditioning potential on the gate rises, a false turn-on can occur.
Accordingly, there exists a need for a high speed AND circuit which will enable rapid decoding of an address for a memory array. Furthermore, there exists a need for a high speed rapid decoding circuit for a memory array to enable optimum operation of the array.
Exemplary prior art indicating CMOS logic circuits can be found in IBM Technical Disclosure Bulletin, Vol. 27 No. 6, Nov. 1984, pages 3200, 3201, and U.S. Pat. No. 3,443,112 to Bowers, Jr., U.S. Pat. No. 3,500,062 to Annis, U.S. Pat. No. 4,185,209 to Street, U.S. Pat. No. 4,233,524 to Burdick, U.S. Pat. No. 4,511,814 to Matsuo et al., U.S. Pat. No. 4,577,124 to Koike, U.S. Pat. No. 4,590,393 to Ransom et al. and U.S. Pat. No. 4,620,117 to Fang.
Representative prior art showing decoding circuits can be found in IBM Technical Disclosure Bulletin, Vol. 8, No. 4, Sept. 1965, pages 642,643, and U.S. Pat. No. 3,344,005 to Stewart, U.S. Pat. No. 4,429,374 to Tanimura, U.S. Pat. No. 4,618,784 to Chappel et al., and U.S. Pat. No. 4,684,829 to Uratani.
Accordingly, it is an object of this invention to provide an improved logical AND circuit.
It is a further object of this invention to provide an improved decoding circuit for high speed memory operation for both access and cycle.